Argonne National Laboratory

Upcoming Events

9th International Front-End Electronics Conference

May 20, 2014 8:00AM to May 23, 2014 5:00PM
Building 241
The 9th International Front-End Electronics (FEE) Conference will be held at Argonne Tuesday, May 20, through Friday, May 23, 2014. The conference will take place at the new Energy Sciences Building, ESB 241.

Keynote Speakers

Tuesday, May 20, 2014

8:40 a.m. – 9:40 a.m.

X-Ray Detectors: Status and Future Needs
Mark Rivers, The University of Chicago CARS

Wednesday, May 21, 2014

8:30 a.m. - 9:30 a.m.

Quanta Image Sensor (QIS) - an oversampled visible light sensor
Eric Fossum

Analytical and experimental results with the Digital Integration Sensor (DIS) and with the Quanta Image Sensor imaging concepts, including dynamic range extension and realization, are reported. The “quantized” DIS (qDIS) concept is also proposed. The continuum between the conventional CMOS APS, the DIS, the qDIS and the QIS is discussed as a sort of roadmap, along with trades in power and performance enhancement. Imaging performance metrics of single-bit and multi-bit photo-electron-counting Quanta Image Sensors (QIS) are analyzed using Poisson arrival statistics.

Signal and noise as a function of exposure are determined. Simulation of binary data acquisition and image formation was performed. Initial analysis and simulation of a readout signal chain has been performed and bounds on power dissipation established. Photodetector device concepts have been explored using TCAD. The D-log H characteristic of single-bit sensors including overexposure latitude is quantified. Linearity and dynamic range are also investigated. Read-noise-induced bit-error rate is analyzed and a read-noise target of less than 0.15 e- rms is suggested.

Wednesday, May 21, 2014

2:00 p.m. – 3:00 p.m.

Low Power Robust Design of FinFET-based Circuits using a Technology-Circuit Co-optimization Approach
Professor Sumeet Gupta, Penn State

Transistor scaling has been the main driving force for the success of the semiconductor industry for the past several decades. However, sustaining the benefits of scaling with conventional bulk MOSFETs has proved to be extremely challenging due to prohibitively large increase in short channel effects and sensitivity to process variations. As a result, alternative technologies with higher scalability are being explored, amongst which FinFETs have emerged as the most promising substitute for the standard transistors. However, FinFETs have their own limitations and design issues like width quantization and higher front end capacitance due to their non-planar structure. Hence, using FinFETs as a drop-in replacement for the bulk MOSFETs is expected to yield sub-optimal designs.

In order to harness the full potential of FinFETs, there is a need to explore technology-aware circuit design techniques, which utilize the unique features of FinFETs to achieve superior design solutions. In this talk, I will present several such techniques with a focus on low power robust design of memories and digital logic. I will start my talk by introducing the device structure and characteristics of FinFETs and the circuit implications of making a transition from bulk MOSFETs to FinFETs. I will, then, present technology-circuit co-design techniques based on symmetric and asymmetric spacer optimization, asymmetric source/drain doping, fin orientation and independent gate control of FinFETs.

I will highlight the importance of considering device-circuit interactions to achieve higher energy efficiency and stability of FinFET-based memories and logic. I will also briefly discuss the implications of some of the techniques on analog circuit design. Finally, I will present the simulation framework that we have developed for FinFET-based circuits in sub-10nm technologies and discuss its key features.”


The meeting will provide an opportunity to discuss the front-end electronics for future HEP experiments as well as for upgrades to existing ones, for astrophysics, medical instrumentation, photon science and in the field of CMOS Monolithic Active Pixel Sensors.

Recently, there have been very interesting developments in 3D vertically integrated pixels and electronics, which promise to have a major impact on the design of future detectors. The FEE 2014 meeting will be an excellent opportunity to discuss these developments and exchange new ideas.

Meeting themes will include:

  • Front-end circuits and signal processing for particle physics, photon science, nuclear, medical and space applications;
  • Monolithic Active Pixel Sensors (MAPS);
  • Vertical integration processes and fine-pitch interconnection techniques;
  • Homogeneous and heterogeneous 3D integrated circuits;
  • SOI detectors;
  • Deep submicron technologies and radiation tolerance.

Participation will be by invitation of the Organizing Committee. If you are interested in the Meeting and you have not been invited, please contact the organizing committee at or call 630-252-6250. Visit the Conference Website for more information.