Abstract: Data-flow computing with field-programmable gate arrays (FPGAs) is promising for further scaling computational performance after performance improvement by multi-core scaling becomes difficult. In our laboratory, we have developed a system with FPGAs and a data-flow compiler that generates a pipelined custom hardware module to be embedded onto an FPGA and executed as stream computing.

In this talk, I talk about the system, the data-flow compiler, and a case study of FPGA-based tsunami simulation, following the recent trend of FPGA application for high-performance computing, in addition to recent updates using Intel’s OPAE.