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Workshop | Mathematics and Computer Science Division

International Workshop on Machine-Learning Hardware

The IWMLH workshop is a forum for learning and engaging on those aspects. It is as part of the Digital ISC2020 conference offering - videos will be made publicly available starting from the 22nd of June and a live Q/A session will be held on the 25th.

Recent years have seen a surge of investment in AI chip companies worldwide. Most companies design accelerators for industrial applications, as opposed to scientific workloads. As the use of machine learning (ML) accelerates in the HPC field itself, there is concern that the scientific community should influence the design of this new specialized hardware. Indeed, scientific computing has an uncommon set of requirements regarding platform usage and administration, and how those chips answer those demands will shape the future of their integration within the global scientific computing infrastructure.

The IWMLH workshop (https://​mlhard​ware​.github​.io/) is a forum for learning and engaging on those aspects. It is as part of the Digital ISC2020 conference offering - videos will be made publicly available starting from the 22nd of June and a live Q/A session will be held on the 25th. The workshop will feature a keynote speech from Albert Cohen (Research Scientist, Google Research) on the associated compilation challenges, as well as presentations from select AI accelerator companies from the U.S. and Japan (Groq, SambaNova, GraphCore, Cerebras, Preferred Networks).

Feel free to watch the videos that will be uploaded on the workshop website starting on the 22nd and join us for our live Q/A on the 25th by using the public slack invitation widget at https://​mlhard​ware​.github​.io/.

Industrial presenters will give an overview of their solutions regarding the following aspects:

  • Programming models. Most AI chips are designed to leverage regularity in the dataflow inherent in ML models. This design supposes the use of standard model representation formats and/or custom dataflow graph formats. Those programming models are of high interest to the scientific community. We need to understand which types of ML/scientific applications will be supported by each platform, as well as the associated development and maintenance costs.
  • Compiler toolchain. ML accelerators often rely on complex compilation technology to map dataflow descriptions to hardware. These compilers can be radically different from existing compiler stacks in that they may solve complex placement and routing problems. The usage model of those compiler toolchains in a scientific computing context is a subject worthy of discussion. Indeed, the features of the compilers and constraints around their use will play a large role in the scientific process itself.
  • System interfaces. Understanding what low-level system interfaces will be available can help cast light on which usage and administration model to expect. In particular, we’d like participants to discuss expected capabilities in terms of concurrency, partitioning, debugging, power management, and performance characterization.
  • Architecture. Successful integration of AI chips in the existing scientific computing infrastructure will require a proper understanding of chips in terms of operator optimization and customization, bandwidth, latency, memory management, power demands, and network capabilities.

Participating Companies

Adrian Macias, Machine Learning Systems Specialist.

Kunle Olukotun, Chief Technologist and Co-Founder.

Matt Fyles, VP of Software.

Andy Hock, Senior Director and Head of Product.

Yusuke Doi, VP of Computing Infrastructure.

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