Abstract: There has been a rapid rise of massive parallelism in modern processors, as exhibited by the astonishing growth of compute cores. In contrast, memory bandwidth lags behind significantly, causing an ever-growing gap between off-chip memory bandwidth and the cumulated computing power in a machine. Such a gap leads to a host of challenging issues. For example, it causes an explosion of recently accessed datasets with temporal locality of very short duration and spatial locality of different strides. Such patterns have led to congested memory accesses in the memory pipeline, stalling the warp schedulers and degrading the performance. Hence, there is a critical need of a cache-memory concert that can orchestrate cache and memory management to meet the challenges of massive parallelism.

This talk will cover our recent research to orchestrate a cache-memory concert. First, I will present a divergence-aware scheme that can orchestrate L1D cache management and warp scheduling together for GPGPUs. Then I will describe the development of a cutting-edge warp-scheduling algorithm that can predict the resource demand of active warps and throttle the consumption of load-store units for effective warp parallelism.

Bio: Weikuan Yu is a professor in the Department of Computer Science at Florida State University.His research interests include processor-memory architecture, data analytics in social networks, high-speed interconnects, cloud and distributed systems, storage and I/O systems.

This seminar will be streamed.