Franck Cappello, a senior computer scientist in the Mathematics and Computer Science Division at Argonne National Laboratory, has been named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).
The society states that “recognizing the achievements of its members is an important part of the mission of the IEEE. Each year, following a rigorous evaluation procedure, the IEEE Fellow Committee recommends a select group of recipients for elevation to IEEE Fellow. Less than 0.1% of voting members are selected annually for this member grade elevation.”
At Argonne, Cappello leads research on fault tolerance, lossy compression, and reconfigurable architectures for emerging extreme-scale platforms. He is also director of the Joint Laboratory on Extreme Scale Computing, an international organization gathering six of the top supercomputing institutions in the world, whose goal is to address science and engineering’s most critical needs in extreme-scale simulations and data analytics and take advantage of the continuing evolution of computing technologies.
Cappello has made pioneering contributions to the field of parallel and distributed computing. One of his most notable achievements was Grid’5000, a large-scale, highly reconfigurable experimental testbed to perform controllable and reproducible parallel and distributed computing experiments. This platform, designed in 2003, is still in operation and has enabled hundreds of scientific publications. He also developed and directed the MPICH-V project based on the Argonne-developed MPICH software that started 16 years of fundamental and applied contributions in fault tolerance for high- performance computing. Recently, Cappello initiated new research at Argonne on lossy compression for scientific datasets and reconfigurable computing in the context of the post-Moore era. The compression research has led to best-in-class lossy compressors strictly respecting user-set error controls. The reconfigurable computing research is a long-term effort to find relevant solutions for significant performance improvement when CMOS technology reaches its scaling limits.
“I am deeply honored to be named a Fellow of this prestigious organization, and I thank my colleagues who have enabled me to achieve this recognition,” said Cappello.