Kazutomo Yoshii, a principal software development specialist in Argonne’s Mathematics and Computer Science division (MCS), has organized two workshops to be held December 11 at the 2018 International Conference on Field-Programmable Technology in Okinawa, Japan. The workshops are an extension of ongoing international collaboration supported by the Joint Laboratory for Extreme-Scale Computing, led by Franck Cappello (MCS) and the DOE USA and MEXT Japan Collaboration on Extreme Computing, led by Pete Beckman (MCS).
Both workshops address the issue of how researchers can improve the performance and energy efficiency of computation by exploiting the power of field-programmable gate arrays (FPGAs) for future high-performance computing (HPC) systems.
The morning workshop will focus on the feasibility of integrating HPC with FPGAs. Such an integration is needed so that HPC platforms – traditionally designed to address floating-point-intensive workloads – can also accommodate the new requirements of big data and data analytics.
“Since FPGAs have already demonstrated their acceleration potential for these new HPC requirements, integrating FPGAs into HPC is a natural step,” Yoshii said.
It is not, however, a trivial step. Yoshii noted that while FPGAs-accelerated systems are becoming practical in the cloud and in data centers, they are still not common in large HPC systems. The afternoon workshop will examine topics ranging from programming models and network/storage acceleration to clustering technologies that can make reconfigurable high-performance computing practical.
The workshops will include experts from major research institutions, universities, and industry worldwide. Thirteen invited speakers will talk about their cutting-edge research. Approximately 70 attendees are registered for the workshops. The objective is to provide an opportunity to discuss the challenges, accomplishments, and opportunities of code signing FPGAs and HPC production platforms.
For more detailed information about the two workshops, see: https://collab.cels.anl.gov/display/HPCFPGA/HPC-FPGA andhttps://collab.cels.anl.gov/display/RECONFHPC/RECONF-HPC