Skip to main content
Quantum Information Science

Design of radio-frequency readout and controls for mid to large quantum information systems

The project will develop and deliver hardware, firmware and software to read out and control a multi-qubit system. The system will query about qubit states and will control qubit errors in real time.
Typical readout and control interface to the cold electronics, qubits and field-programmable gate array. This device will be used as the initial platform for readout and control of quantum information systems.

This proposal focuses on the development of a warm radio-frequency electronic readout and control (RF-R&C) to achieve quantum error correction (QEC) of a large quantum correction. Development of this dynamic modular system will focus on the following topics:

  • Develop proof-of-concept design for RF and controls that enable large-scale QEC.
  • Allow QEC to run and stabilize qubits for a time much longer than the time required to eventually perform interesting quantum correction algorithms.
  • Minimize latency to maximize number of QEC operations.
  • Implement multiplexing of the control lines.
  • Develop interface and control quantum memories.

A quantum correction program is made of sequential control pulses applied to the inputs. As in a standard computer program, most useful quantum correction programs require conditional branching. Hence, qubit readout and control systems must prioritize hardware latency, fast qubit state detection and control. The readout must be connected to the control of the qubits in a tight feedback loop. To perform those functions, we will use ultra-fast field-programmable gate arrays (FPGAs), analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The hardware platform is based on the Xilinx ZCU111. We will develop readout and control tools fully utilizing the resources of the hardware.  The ZCU111 has been developed around the Xilinx XC7ZU28 FPGA. This FPGA incorporates eight 12-bit ADCs running at 4 Gs/s and eight DACs running at 6.5 Gs/s. The roundtrip latency, including the ADC, DAC and logic interfaces, has been measured to be 100 ns, making possible total latencies of less than 200 ns for feedback control. The FPGA also has about 1 million logic gates, half a million logic blocks and 70 Mb of internal memory. All that functionality combined with more than 4,000 digital signal processors will allow the implementation of complex QEC algorithms.

We will also develop the appropriate RF hardware to interface to test qubit systems. The qubits will be supplied by our collaborators. The number of qubits to be controlled by the electronics will incrementally increase. A ZCU111 board can control up to seven qubits. The design easily scales to a larger system by using more boards.