Enabling Energy-Efficient Artificial Intelligence Hardware with Spintronics

Abstract: The pursuit of high-performance and energy-efficient computing for artificial intelligence (AI) opens up exciting opportunities for emerging memories and unconventional architectures such as analog in-memory computing (IMC). To maximize the potential of such emerging computing technologies, innovations across the stack (from devices to systems) are needed.

In this talk, I will share some of our group’s recent co-design efforts in exploiting spintronic components for developing efficient deep neural network (DNN) hardware. First, a multi-level spintronic synaptic device based on a composite magnetic tunnel junction (MTJ) is proposed and analyzed in simulation. By integrating a standard MTJ free layer exchange coupled with a granular magnetic nanostructure, multiple near-continuous nonvolatile resistive states can be induced thanks to the distribution of the energy barrier among individual magnetic grains.

Second, we exploit stochastic MTJs as the core components for the array-level partial sums (PS) in crossbar architecture and for the processing engines in near-memory systolic arrays. Leveraging the probabilistic switching of spin-orbit torque MTJs, the proposed PS processing eliminates the costly Analog-Digital Conversion in crossbar IMC, leading to significant improvement in energy and area efficiency. We further show that the accuracy loss due to quantization error can be mitigated by a newly developed PS-quantization-aware DNN training methodology.

Our device-to-system co-optimization research demonstrates exciting opportunities for spintronics in developing next-generation energy-efficient intelligent computing systems. I will conclude my talk with discussions on the potential of co-designing spintronics for various unconventional computational functionalities.

Refreshments will be served.